PCB Signal Integrity Simulation for Every Board: S-Parameters, TDR, and Eye Diagrams in Flux
PCB signal integrity simulation in Flux puts full-wave electromagnetic analysis inside the design workflow. Ask Flux to simulate routed copper, review S-parameters, TDR, crosstalk, and eye diagrams at rates up to 20 Gbps, then change the routing and simulate again. Signal integrity review belongs on every board, not only the most expensive ones.
A startup building an industrial camera can have USB 3, PCIe, Ethernet, MIPI, and DDR signals on one compact board. Those interfaces share space with power, connectors, mounting holes, and the enclosure. The team needs to know how the routed signals behave in that physical design. Flux brings the analysis and the edits into the same project, so the engineer can direct the work and use the results to make the next decision.
What the simulation shows
Full-wave electromagnetic simulation analyzes the routed copper and stackup. For a differential pair, ask for SDD11 to examine reflection, SDD21 to examine transmission, and Zdiff for differential impedance. Ask for TDR to see impedance against time and distance, an eye diagram to inspect the signal opening at a specified bit rate, or crosstalk to see coupling between nearby nets.
These results answer different questions. A pair can be routed to a target impedance, while a TDR plot helps the team find where the impedance changes along the route. SDD21 shows transmission across frequency. An eye diagram brings the channel response into the time domain. Together they give the team a practical basis for deciding what to change.
Simulate, change, and simulate again
Start with a routed net or pair. Name the endpoints, frequency range, and measurements you want. Flux runs the simulation and returns the results. If the result points to a geometry change, ask Flux to adjust the route or retune the pair, then run the analysis again. The same conversation connects the engineering question, the layout change, and the new result.
Flux can route differential pairs to a target impedance and tune lengths to an absolute value or match one net to another. Give a tolerance and a skew target; choose trombone, accordion, or sawtooth meanders. For a DDR, QSPI, or SDIO bus, ask Flux to match lanes to a reference. For dense packages, ask for BGA fanout and configure blind, buried, or microvias in the stackup. Read more about routing with Flux and the routing workflow.
From the stackup to the complete device
A four-layer startup board
A small team routes a USB 3 pair on a four-layer sensor board. It asks Flux to evaluate differential impedance and transmission along the routed pair, then adjusts the geometry and runs the simulation again. The team can review the result in hours in Flux, instead of moving between separate design and analysis workflows over days.
A connector breakout
A hardware engineer routes a PCIe pair from a dense connector to a processor. The engineer asks for SDD11, SDD21, and an eye diagram at the lane rate, then asks Flux to refine the pair and repeat the analysis. The plots give the review a shared reference tied to the routed board.
A mounting boss near a high-speed route
A mechanical engineer moves an enclosure boss to improve assembly access. The board needs a new route around the mounting hole. The engineer asks Flux to change the route and review its impedance and eye diagram. Electronics and mechanical teams can make the fit decision with the signal result in the same project.
A smaller enclosure and a new board outline
A product team reduces the size of an enclosure for an Ethernet-connected device. Flux updates the mechanical design and board outline. The team asks Flux to refine the affected routing and simulate the pair again, so the board and enclosure can be reviewed together.
Signal integrity is one part of the electrical review. Flux can also analyze power delivery network impedance with SPICE and vendor capacitor models that include ESR and ESL. See the simulation documentation and our routed-board simulation examples.
Prompts to try
- “Analyze the USB differential pair from the connector to the controller. Show SDD11, SDD21, Zdiff, and TDR.”
- “Plot an eye diagram for the PCIe lane at 10 Gbps. Report the eye height and width.”
- “Analyze crosstalk from the clock to the adjacent data net. Adjust the route, then simulate it again.”
- “Route the DDR data lanes as a length-matched bus to the strobe within 0.25 mm.”
- “Move the enclosure boss away from the connector, update the board outline, and review the affected pair.”
- “Shorten the enclosure, refine the Ethernet routing around the mounting hole, and simulate the new pair.”
Frequently asked questions
It analyzes how signals behave in the routed board. Flux can show impedance, S-parameters, TDR, eye diagrams, and crosstalk.
SDD11 describes differential-mode reflection. SDD21 describes differential-mode transmission through the pair.
Yes. Ask Flux for an eye diagram at a specified bit rate up to 20 Gbps, with eye height and width.
Yes. Ask Flux to refine the geometry or tune the route, then simulate again to review the change.
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